It is known that in bipolar transistors the cut-off frequency f.sub.T, which is a guide to high speed operational properties, increases as the base region becomes thinner. Furthermore, as the size of the transistor becomes reduced, the parasitic capacitance is reduced and operational speed becomes faster. Ion implantation is used as a method of forming thin base regions, but there is a limit to how thinly impurity ions can be implanted. Furthermore, with the ion implantation method, it is necessary to eliminate displacement of silicon atoms of the lattice, in other words lattice defect of the single crystal silicon, resulting from the implanted ions. For this purpose, the annealing process is performed by heating to a high temperature. However, in the annealing process, the implanted impurities are diffused. As a result, the thickness of the base region inevitably increases by this amount.
A low temperature epitaxial growth method is known as a technique for forming thin base regions. A bipolar transistor and a method of its production, employing this method, is described in Japanese Patent Application Laid-Open Publication No. H4-330730.
With reference to FIG. 1 which is a cross-section of the semiconductor device, the structure of the bipolar transistor described in the above-mentioned publication is as follows.
An N.sup.+ -type buried layer 202 in which the impurity is arsenic is selectively formed on the surface of a P.sup.- -type single crystal silicon substrate 201 having a resistivity of 10 to 15 .OMEGA.cm. The surface of the P.sup.- -type single crystal silicon substrate 201 is covered by an N.sup.- -type silicon epitaxial layer 203 which has a thickness of approximately 1.0 .mu.m and an impurity concentration of approximately 5.times.10.sup.15 cm.sup.-3. Field oxide films 204 and 204a for element isolation, which reach either the P.sup.- -type single crystal silicon substrate 201 or the N.sup.+ -type buried layer 202, are formed by a known selective oxidation method in the N.sup.- -type silicon epitaxial layer 203. The field oxide film 204 isolates the bipolar transistor. One of the N.sup.- -type silicon epitaxial layers 203, which are surrounded by the field oxide film 204 and are divided off by the field oxide film 204a, is transformed into an N.sup.+ -type collector drawing region 205 by phosphorus diffusion. In this way the silicon substrate or body 206 is constructed.
The top surface: of the silicon substrate 206 is covered by a silicon nitride film 207. An opening 214 which reaches the N.sup.+ -type collector drawing region 205, and an opening 243 which reaches the N.sup.- -type silicon epitaxial layer 203 are provided in the silicon nitride film 207. The opening 214 is filled with an N.sup.+ -type polycrystalline silicon film 212 which is connected to the N.sup.+ -type collector drawing region 205 and constitutes a collector drawing electrode. The top surface of the silicon nitride film 207 in the vicinity of the opening 243 is covered by a base drawing electrode P.sup.+ -type polycrystalline silicon film 211 which has a protrusion of a width D extending in the direction inside the opening 243. The silicon nitride film 207 and the polycrystalline silicon films 211 and 212 are covered by a silicon oxide film 213. An opening 241 is provided in the silicon oxide film 213 and the above-mentioned P.sup.+ -type polycrystalline silicon film 211 immediately above the opening 243, and a first spacer 219 comprising a silicon oxide film is provided on the side surface of the opening 241.
The top surface of the N.sup.- -type silicon epitaxial layer 203 which is exposed in the opening 243 is covered by a P-type single-crystal silicon layer 221 which is an intrinsic base region, and the lower surface of the P.sup.+ -type polycrystallinesilicon film 211 which is exposed in the above-mentioned protrusion is covered by a P-type polycrystalline silicon film 222. The P-type single-crystal silicon layer 221 and the P-type polycrystalline silicon film 222 are selectively formed on the surfaces of a single-crystal silicon layer and a polycrystalline silicon film by low temperature epitaxial growth. The top surface of the P-type single crystal silicon layer 221 and the lower surface of the P-type polycrystalline silicon film 222 are connected to each other. The lower surface and at least part of the side surface of the spacer 215, part of the top surface of the P-type single crystal silicon layer 221 and the side surface of the P-type polycrystalline silicon film 222 are covered by a second spacer 225 comprising a silicon oxide film. An N-type single crystal silicon layer 226 which is an emitter region which covers the top surface of the P-type single crystal silicon layer 221, is filled in a space formed in the spacer 225. Openings which respectively reach the P.sup.+ -type polycrystalline silicon film 211 and the N.sup.+ -type polycrystalline silicon film 212 are provided in the silicon oxide film 213. On the top surface of the silicon oxide film 213 are provided a metal electrode 231 which is connected to the N-type single crystal silicon layer 226, and metal electrodes 232 and 233 which are connected via openings formed through the silicon oxide film 213 to the P.sup.+ -type polycrystalline silicon film 211 and the N.sup.+ -type polycrystalline silicon film 212 respectively. The metal electrodes 231, 232 and 233 are made of aluminum or the like.
In the bipolar transistor mentioned in the above-mentioned publication, it is possible for the film thickness to be thinner than that of an intrinsic base region formed by ion implantation. However, there is the following problem.
This problem relates to parasitic capacitance. Insulating isolation between the P.sup.+ -type polycrystalline silicon film 211 which constitutes the base drawing electrode and the N.sup.- -type silicon epitaxial layer 203 which constitutes part of the collector region is performed by a silicon nitride film 207. In order that the P.sup.+ -type polycrystalline silicon film 211 and the P-type single crystal silicon layer 221 which is the intrinsic base region are satisfactorily connected, it is not preferable that the film thickness of the silicon nitride film 207 be greater than the sum of the film thickness of the P-type single crystal silicon layer 221, which is selectively grown epitaxially, and the film thickness of the P-type polycrystalline silicon film 222 which is selectively grown at the same time. If the film thickness of the P-type single crystal silicon layer 221, which is the intrinsic base region, is reduced in order to improve the cut-off frequency f.sub.T, naturally the thickness of the silicon nitride film 207 must be reduced. In this case, the parasitic capacitance formed between the base region and the collector region increases, and the transistor performance is lowered.